In the field of digital circuit design, flow control signals are used to manage the rate of data transmitted between two nodes of a chip (flow control). One objective of flow control is to prevent a relatively fast sender node from overwhelming a relatively slow receiver node with data. For example, the receiver node may receive a heavier traffic load than the sender node, or the receiver node may have less processing resources than the sender node. In another example, the receiver node may have a queue with a limited size. When the sender node transmits data too rapidly, the queue will become full and unable to store subsequent transmissions (overflow). A receiver node with a full queue will send a flow control signal to the sender node to cause the sender node to stop transmitting data to the receiver node until there is sufficient room in the queue.
An RTL (register-transfer level) abstraction is used by hardware description languages (HDLs) to generate lower-level logical representations of digital circuits modeled by an RTL description. Verilog and VHDL are two of the most common HDLs used today. Using HDLs, designers declare the registers and describe the combination logic using constructs such as if-then-else and arithmetic operations. An RTL description is typically converted to a gate-level description of the digital circuit using a logical synthesis tool. The gate-level description is then used by placement and routing tools to generate a physical layout, and logical simulation tools may be used to verify the integrity of an RTL description. An RTL description typically consists of a hierarchy of modules. The modules communicate with each other using a set of declared input, output, and bidirectional interfaces. A module may perform a particular function, or store and/or transmit signals (e.g., data) to other modules, for example.
After the functional blocks of a chip have been modeled using RTL, for example, the design process proceeds to the physical design stage, which may include routing, timing analysis, and timing closure stages. Based on position, orientation, and routing decisions for functional blocks made during the physical design stage, functionally identical functional blocks may experience different signal delays/latency when transmitting data between blocks. At this stage in the design process, certain aspects of the chip design, such as buffer size, are locked-in or “frozen” and cannot be changed or adjusted without considerable time and effort to redesign the physical layout of the chip. Therefore, it is more desirable to introduce a signal delay at the chip-level to prevent buffer overflow rather than redesigning the physical layout of the chip.